Configuration pins
TDO is a JTAG in circuit testing pin which is not being used here,so can be made to float
M0,M1,M2
As the configuration comes in serially M[2:0]=%111.This is infact set externally by wiring these pins to +5v as
shown on the schematic,so the pins can either be set to float or pulled up.
Done
The 'FPGAIt' software relies on the DONE pin changing state when configuration has finished,so it should be set to be pulled up.
Perform CRC during configuration
The software can be made to embed a CRC in the bitstream,which is recommended so that any problems uploading the design to the FPGA will be spotted by the software.
Produce ASCII configuration data
The configuration data must not be ASCII to be understood by 'FPGAIt',leave this off.
5v tolerant I/Os
This is only relevant when using the XC4000XLA and XC4000XV series,and would depend on the application whether you want the I/O pins to be 5v tolerant or whether you want to use the device in low power mode.
Synchronize startup to DONE input pin
This option allows the startup to be activated by asserting the bidirectional 'DONE' pin,as opposed to a number of transitions of the CCLK pin (see below).When configuring the FPGA from a BBC Micro the CCLK is used to start the design so do not select this option.
Output events
Three things happen after the '.bit' file has been sent to the FPGA,and the order can be set to occur from one to four CCLK deges after the end of configuration.
"Done" should be set to change state last (eg.use C3 for 3 CCLKs after the end) so the BBC Micro can detect the DONE pin changing when the design has started.
"Enable output" should occur earlier than the DONE transition.It's when the pins become active - so there must be no outputs wired to FPGA pins which are about to be made outputs too,as this would cause a conflict.
"Release set/reset" should occur earlier than the DONE transition.It frees the set and reset lines to all the flip flops inside the FPGA and may be important if a state machine (for example) in the FPGA needs to be reset before the outputs become active,in which case "Enable output" should be set to some time after "Release set/reset" but before "Done".
