6502 processor core in VHDL
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The Free-6502 core is a 6502 compatible CPU core.Its basic features are:
- 6502 binary code compatible.
- Written in 100% VHDL.
- Simple synchronous 8-bit bus interface.
- Entirely synchronous design.
- Registered I/O for simple porting and integration.
- Supports all standard 6502 instructions.
It is based on version 0.7 of the Free-6502 with a little additional work to implement BCD mode arithmetic,plus a slightly repackaged version of the VHDL ready to use with the Xilinx Foundation M1.5 software.
For use with the Xilinx Foundation M1.5 software download the soft6502 project.This should be unzipped into the C:\fndtn\active\projects\ per usual.It contains a simple schematic using the core and the testrom and some i/o buffers.This can be used as a basis for other designs or at the very least as a quick way to evaluate the core: it's literally "take it out of the box and use it".
For use with other tools start with the pure VHDL original.
One of the slightly amusing parts of the design is the use of an Excel spreadsheet to describe the microcode,which is then exported and recycled into the VHDL required for the CPU core.
With no special care taken towards optimising for area or speed,the default settings in the Xilinx Foundation M1.5 software produced a design with the characteristics as follows.
Implemented at 12.5MHz (using only a clk period constraint)
- Free6502 core only
Used 563 CLBs (from 784 in a 4020XL-PQ160-2),71% full
- Free6502 core with my test ROM also
Used 607 CLBs (from 784 in a 4020XL-PQ160-2),77% full
©2003 SPROW [Created 11-Oct-2003] | home
