Implementation sub options
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The first tab is used to define how the map software treats the design:
Logic optimizations options
"Trim unconnected logic" option will optimise away any unused logic.In the case of this example design the 'ripple carry out' pin is unused and the compiler will spot this,remove it,and the logic used to generate the ripple carry out.In larger designs it is useful for spotting errors as it'll optimise huge chunks of the design away which would otherwise have gone unnoticed.Turn it on.
"Replicate logic to allow logic level reduction" this gives the compiler permission to try out adding a few gates here and there in the hope that suddenly an optimisation can be made,for example:
"Generate 5 input functions"
When enabled the F and G functions within each CLB can be used in conjunction with a spare multiplexor in the CLB to make a large 5 input function rather than the normal 3 input ones.It makes the design use less gates,but runs slower as a trade off.
Map options
"CLB packing strategy" usually left as 'fit device',but you may wish to experiment with other packing strategies.
"Pack CLB registers for" structure,speed,or area.Again,it may be worth experimenting with CLB register packing strategies
"Pack I/O registers/latches into IOBs".When off,any registers and latches after the main logic function but before the I/O pad will be forced to be kept in CLBs within the FPGA core.Otherwise it permits the compiler to move them into the IOBs which can free up space in the core for more of the main logic function.
"Use generic clock buffers instead of BUFGPs and BUFGSs" should be selected if there are primary clock buffers (BUFGPs) or secondary clock buffers (BUFGSs) used in the design but aren't actually supported by the chosen FPGA technology.It could be useful if trying to move a design from one Xilinx FPGA family to another.
This tab sets up what the place and route software can do:
Place and route effor level
Basically,the more effort,the better the result,but the longer it takes.
Router options
These figures set up how many itterations the software will make in an attempt to meet any constraints that have been set.It is possible to set it so high that the compiler will never succeed and just oscillate - making the timing better then worse then better again but never actually reaching a conclusion.
Use timing constraints during place and route
This should be turned on for the timing constraints in the '.ucf' file to be taken into account.
This tab sets up what type of timing analysis is performed,if it was enabled in the implementation options window.
For the software provided on the Prentice-Hall CD,leave the contents of this tab unchanged.
©2001 SPROW [Created 10-Feb-2001] | home
