FPGA workshop

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A design to start with

What is always needed to gain confidence with a new device is a simple demo circuit which performs a trivial task just to prove that the device is alive and that all the stages of the design are working reliably - it's a bit like building the VU bars PIC project to check that you understand how to use the PIC assembler and PIC programmer before moving on to a more complex design.

Though many vendors such as Lucent,Atmel,Oric all produce FPGAs which will do the same job the product offering from Xilinx is the only one covered here because it is their software that comes on the cover CD of a book on FPGAs.Without this you will almost certainly find that the cost of the software tools make FPGAs something beyond the reach of the home electronics constructor.

Here,we'll start by using the highly flexible and completely reconfigurable FPGA as a simple 4 bit counter.This will aid as a handy tutorial to the FPGA design software and building some working hardware:

Operation of the circuit is as follows:

A reset occurs when RESET is held low
When the CLK rises during a reset the count is loaded to %0100 on CLK's next rising edge
The count then advances on every rising edge of CLK
At any moment the count value QA,QB,QC,QD and NOTRESET are output

This can also be described by the following timing waveform:

Shopping list of what you'll need

Here is a complete list of what you should need to follow the counter example on this page and ultimately go on to create your own programmable logic solutions:

Prentice-Hall book and CD ROM "The Xilinx Practical Designer" ISBN0130205869
A small 4000 series Xilinx FPGA,the example here uses a 4005E-PC84-4
Veroboard for wirewrapping or a PCB
An 84 pin PLCC wirewrapping socket
A length of 20 way ribbon cable and female 20 way IDC plug
Solder,hand tools
A BBC micro with disc interface
A ZIP file of the Xilinx project described here
FPGA image uploader software and software to use as a clock source for the counter

Opening the design

Having installed the software,taking care to have read the software warnings,you can unzip the demo project you downloaded.Extract from the zip into the path "C:\fndtn\active\projects\" directory so you end up with something like:

C:\fndtn\active\projects\
	demo.pdf
	demo
		design files

Start the 'Xilinx Foundation Project Manager',and when the 'Getting started' window appears choose 'demo' from the list.After a bit of grinding the demo project will be opened and it is ready to compile.

First,you might want to go and have a look at the design by clicking on the 'Schematic Entry' icon in 'Project Manager',

this will open the first (and only) page of the design and should look just like the schematic above.

Close the schematic editor and go for an implementation.

Implementing the design

If prompted that the netlist from the schematic editor is newer than the current project netlist click 'Yes' to update it - this just brings the compilers copy of the design into sync with any changes you made with the design entry software.

Check the device is 4005E and the speed grade is 4.You can change this from 'Xilinx Foundation Project Manager' from File > Project Type,but the changes wont come into effect until you next come to compile the design.

Xilinx's bizarre version control can be overridden if necessary - they see revisions as major changes and versions as minor changes.Note that the sources aren't copied into the new version/revision directory you're about to create so it's a bit pointless doing anything but rev1 ver1 unless you manually copy the sources across since you'd have no way of going backwards at a later date!

The 'Options' button should be consulted to check that no silly defaults have been set which will stop your design working - the options you choose are only remembered until you quit 'Xilinx Foundation Project Manager':

Option:	Action required:	Comments:
User constraints	Enter the filename for the constraints file called '<projectname>.ucf' if there is one	For large designs it is sometimes a good idea to run the compiler with timing constraints but no pin constraints to see where the compiler thinks the pins are best placed for best speed.These can then be used to design the circuit board layout and the pins can be fixed in place in future runs of the compiler by copying and pasting the pin listings from the report file the compiler produces into the user constraints file.
Implementation	Leave at the 'default'	There are many suboptions available by clicking on 'Edit template'
Simulation	Set to 'Foundation EDIF'	Though there are a whole host of other simulation output formats but since the CD which came with thte Prentice Hall book only comes with the Foundation simulator there's no point choosing anything else.
Configuration	Leave at the 'default'	There are many suboptions available by clicking on 'Edit template'
Produce Timing Simulation data	Tick this box if you want to run a timing simulation after your design has been placed and routed in to an FPGA	This option takes a long time,so if you're happy that the design will not need a timing check don't bother enabling this option
Produce Configuration data	Tick this box if you are ready to send the design to your circuit board	If you're just doing an itteration to see if you've fixed some timing problem,don't bother producing a bit file

Choose 'OK' to confirm you are happy with the optins you have set then 'Run' the compiler.

A new window will open with a message box occupying much of the screen - you can see where the compiler is up to and read any warnings it produces.All the test that goes past is captured as a series of reports so it doesn't matter if you can't read it as fast as it goes past!

At the end of compiling the demo project you should consult the reports.They should be similar to these:

ngbuild report - if ngbuild gives an error compilation will stop and you'll have to go and fix it,but if it only gives warnings it will continue.In this case both of the warnings can be ignored,but you should pay careful attention to what ngbuild is warning you about
map report - the counter in the demo project uses 63 gate equivalents
par report - this report gives you a summary of your entire design,including which gates it has optimised away (in this case all the logic associated with the unconnected RCO pin have been removed).Also note that all the output pins are flagged as 'SLEW=SLOW'.
Used pin report - pin useage in this design is assigned in the user contraints file so the signals appear in the pin listings as 'LOCATED'
bitgen report

Uploading and testing the design

Now comes the hands on part - find the file '<projectname>.bit' and copy it to a floppy disc. Copy along with this the BBC micro software for uploading the design and also the clock generating software for the BBC Micro - this will allow you to firstly send the compiler's output into the FPGA then use the computer as a pulse generator too.

Build the following hardware:

Notice the dual use of the nINIT and DIN pins on the FPGA - except for dedicated configuration pins (DONE,nPGM,and CCLK) you get the pins used for configuration back for use as general purpose i/o when configuration is finished.

With the BBC micro user port connected to the FPGA as shown,simply enter: CHAIN"FPGAIt" with the disc in the drive.Supply the filename that you saved the 'demo.bit' file as when prompted and 'FPGAIt' will load and serialise the bitstream for the FPGA then attempt to start the design.

The software contains some error checking and will abort if anything goes wrong,see the manual for the software for hints as to what they might mean.

When configuration completes successfully,the BBC Micro can also be used as a handy clock source (though an external clock source may also be used if available).So with an oscilloscope or a bank of LEDs connected to testpoints TPqa-TPqd as shown in the schematic diagram,simply enter: CHAIN"DIV16SUP" and the counter will run!