FPGA terminology
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The example on this page assumes a 4005E-PC84-4 is being used.
Xilinx part numbers usually consist of
- a family number (4000 series here)
- the offset within the family which tells you how many thousand gate equivalents are available (4005 so it's a 5,000 gate device)
- a suffix telling you what varient of the family it is (E here)
- the package (-PC84 is an 84 pin PLCC package)
- the speed grade (-4 used here,the smaller the number the faster it is).
- sometimes an extra 'C' or 'I' for commercial and industrial grade temperature ranges
Input output blocks (IOBs) are the blocks which interface between the pins on the chip to the FPGA's heart.Just what is in an IOB is dependant on the family of FPGA you're using,but it's usually a mixture of flip flops and buffers.
Configurable logic blocks (CLBs) are the fundamental building block at the heart of the FPGA.A device contains CLBs arranged on a square matrix,each one containing some lookup tables,some muxes,and some latches,though the exact contents are again dependant on the family of FPGA you're using.
Routing resources can be though of as a big box of wires which are all intially unused.As the compiler puts parts of your design in various CLBs within the device it will need a handful of wires to connect it to neighbouring CLBs and to IOBs.There are usually a few special bits of high speed routing for clocks,but be warned - the amount of routing you have is a finite resource!
Whatever method you choose to enter your design it will ultimately need to pass through Xilinx's compiler which consists of several programs which are launched automatically when 'Implementing' the design.These are:
- ngbuild - this collects together all of the source files in one big heap,building them into a giant flattened netlist of the entire design
- map - the takes the netlist from ngbuild and maps it to the chosen device architechture by breaking it up into CLB sized pieces
- par - this assigns locations for all the generic CLBs mapped earlier and wires between them so that the design is now placed and routed into an actual device
- trce/ngdanno - if a timing analysis is requested all of the paths which have been placed and routed will be traced and the timing estimates back annotated to the original netlist produced by ngbuild.This way you can find the delay of a route searching by it's original name that you assigned to the net
- bitgen - this turns the result from place and route into a long sequence of 1's and 0's which is the configuration bit stream that must be injected into the FPGA to set it up to perform your logic design
Before implementing your design you should carefully set the implementation options,especially for 'bitgen' which allows you to set the number of additional configuration clocks needed after the end of the bit stream before the design becomes active - otherwise you may find your FPGA is sucessfully configured but doesn't work because it is waiting for (say) just another 2 clock cycles before it becomes active! It is also possible to skip bitgen (or do it later) if you are just running the compiler to see if your design meets your specifications or fits the device.
Designs targeted at FPGAs are often quoted in 'gate equivalents',which is the number of primitive gates (usually 2 input NANDs) you would have to wire up to get the same functionality as what you have created.
The Xilinx compiler will tell you roughly how many gate equivalents you have used,and may abort the compilation process if it is larger than the number of gates in the device - not always though! Sometimes it is possible to use some special feature of the FPGA's architechture to save a few gates,eg.using flip flops in the IOB rather than in a CLB.
This property attached to a pin (as opposed to SLEW=FAST) marks that that pin is slew rate limited.ie.the pin is not being used at as high a speed as is possible in this speed grade of device.The advantages are lower power - too many fast pins physically near eachother can cause surges which the decoupling capacitors can't damp out.
A user constraints file called '<projectname>.ucf' will exist in the project directory as it is created when the project itself was created.It contains constraints to apply to the design which tell the software a bit more about how the FPGA is being used - so where pins are placed on the PCB,what temperature it is running at,which signals are high speed and what speed they are etc... The default '.ucf' file which is created does nothing,and consists entirely of comment lines (starting with a hash '#' symbol) telling you the syntax of each type of constraint which you can edit in any text editor.
©2001 SPROW [Updated 10-Feb-2001] | home
