Xilinx Mapping Report File for Design "demo" Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design Information ------------------ Command Line : map -p xc4005e-4-pc84 -o map.ncd demo.ngd demo.pcf Target Device : x4005e Target Package : pc84 Target Speed : -4 Mapper Version : xc4000e -- M1.5.21 Mapped Date : Sat Nov 25 14:17:45 2000 Design Summary -------------- Number of errors: 0 Number of warnings: 1 Number of CLBs: 3 out of 196 1% CLB Flip Flops: 5 4 input LUTs: 4 3 input LUTs: 2 Number of bonded IOBs: 7 out of 61 11% IOB Flops: 0 IOB Latches: 0 Total equivalent gate count for design: 63 Additional JTAG gate count for IOBs: 336 Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Design Attributes Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - Added Logic Section 7 - Expanded Logic Section 8 - Signal Cross-Reference Section 9 - Symbol Cross-Reference Section 10 - IOB Properties Section 11 - RPMs Section 12 - Guide Report Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:baste:24 - All of the external outputs in this design are using slew-rate-limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the original design. Please see your vendor interface documentation for specific information on how to do this within your design-entry tool. Note: You should be careful not to designate too many outputs which switch together as fast, because this can cause excessive ground bounce. For more information on this subject, please refer to the IOB switching characteristic guidelines for the device you are using in the Programmable Logic Data Book. Section 3 - Design Attributes ----------------------------- Attribute LOC "P71" on symbol "$I15" "P41" on symbol "$I16" "P15" for signal(s) NOTRESET on symbol "$I19" "P16" for signal(s) QA on symbol "$I3" "P17" for signal(s) QB on symbol "$I4" "P18" for signal(s) QC on symbol "$I5" "P19" for signal(s) QD on symbol "$I6" Section 4 - Removed Logic Summary --------------------------------- 12 block(s) removed 26 block(s) optimized away 12 signal(s) removed Section 5 - Removed Logic ------------------------- The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed. To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). The signal "$I1/RCO" is loadless and has been removed. Loadless block "$I1/$1I107/$I1/RCO" (X_AND2) removed. The signal "$I1/RCO/4.0" is loadless and has been removed. Loadless block "$I1/$1I107/$I1/RCO/4.0/$I1/RCO/4.0" (X_AND2) removed. The signal "$I1/RCO/4.0/2.0" is loadless and has been removed. Loadless block "$I1/$1I107/$I1/RCO/4.0/$I1/RCO/4.0/2.0" (X_AND2) removed. The signal "$I1/RCO/4.0/2.1" is loadless and has been removed. Loadless block "$I1/$1I107/$I1/RCO/4.0/$I1/RCO/4.0/2.1" (X_AND2) removed. The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logic The signal "$I1/Q0/$1I35/A0/2.0" is unused and has been removed. Unused block "$I1/Q0/$1I35/$1I33/$I1/Q0/$1I35/A0/2.0" (X_AND2) removed. The signal "$I1/Q0/CE_S_L/2.0" is unused and has been removed. Unused block "$I1/Q0/$1I70/$I1/Q0/CE_S_L/2.0" (X_OR2) removed. The signal "$I1/Q1/$1I35/A0/2.0" is unused and has been removed. Unused block "$I1/Q1/$1I35/$1I33/$I1/Q1/$1I35/A0/2.0" (X_AND2) removed. The signal "$I1/Q1/CE_S_L/2.0" is unused and has been removed. Unused block "$I1/Q1/$1I70/$I1/Q1/CE_S_L/2.0" (X_OR2) removed. The signal "$I1/Q2/$1I35/A0/2.0" is unused and has been removed. Unused block "$I1/Q2/$1I35/$1I33/$I1/Q2/$1I35/A0/2.0" (X_AND2) removed. The signal "$I1/Q2/CE_S_L/2.0" is unused and has been removed. Unused block "$I1/Q2/$1I70/$I1/Q2/CE_S_L/2.0" (X_OR2) removed. The signal "$I1/Q3/$1I35/A0/2.0" is unused and has been removed. Unused block "$I1/Q3/$1I35/$1I33/$I1/Q3/$1I35/A0/2.0" (X_AND2) removed. The signal "$I1/Q3/CE_S_L/2.0" is unused and has been removed. Unused block "$I1/Q3/$1I70/$I1/Q3/CE_S_L/2.0" (X_OR2) removed. Optimized Block(s): TYPE BLOCK GND $I1/$1I121 VCC $I1/$1I59 VCC $I1/Q0/$1I35/$1I42/$1I40 GND $I1/Q0/$1I35/$1I42/$1I43 VCC $I1/Q1/$1I35/$1I42/$1I40 GND $I1/Q1/$1I35/$1I42/$1I43 VCC $I1/Q2/$1I35/$1I42/$1I40 GND $I1/Q2/$1I35/$1I42/$1I43 VCC $I1/Q3/$1I35/$1I42/$1I40 GND $I1/Q3/$1I35/$1I42/$1I43 VCC $I2/$1I40 GND $I2/$1I43 GND I_from_net_GND AND2 $I1/Q0/$1I30/$1I9 AND2 $I1/Q1/$1I30/$1I9 AND2 $I1/Q3/$1I30/$1I9 VCC I_from_net_VCC AND2 $I1/$1I103 X_OR2 $I1/Q0/$1I70/$I1/Q0/CE_S_L X_AND2 $I1/Q0/$1I35/$1I33/$I1/Q0/$1I35/A0 X_OR2 $I1/Q1/$1I70/$I1/Q1/CE_S_L X_AND2 $I1/Q1/$1I35/$1I33/$I1/Q1/$1I35/A0 X_OR2 $I1/Q2/$1I70/$I1/Q2/CE_S_L X_AND2 $I1/Q2/$1I35/$1I33/$I1/Q2/$1I35/A0 X_OR2 $I1/Q3/$1I70/$I1/Q3/CE_S_L X_AND2 $I1/Q3/$1I35/$1I33/$I1/Q3/$1I35/A0 To enable printing of redundant blocks removed and signals merged, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun map. Section 6 - Added Logic ----------------------- Section 7 - Expanded Logic -------------------------- To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP. Section 8 - Signal Cross-Reference ---------------------------------- To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP. Section 9 - Symbol Cross-Reference ---------------------------------- To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP. Section 10 - IOB Properties --------------------------- NOTRESET (IOB) : SLEW=SLOW QA (IOB) : SLEW=SLOW QB (IOB) : SLEW=SLOW QC (IOB) : SLEW=SLOW QD (IOB) : SLEW=SLOW Section 11 - RPMs ----------------- Section 12 - Guide Report ------------------------- Guide not run on this design.