PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Xilinx PAD Specification File ***************************** Input file: map.ncd Output file: demo.ncd Part type: xc4005e Speed grade: -4 Package: pc84 Pinout by Pin Name: +------------------------------------------------+-----------+--------------+ | Pin Name | Direction | Pin Number | +------------------------------------------------+-----------+--------------+ | CLK | INPUT | P41 | | NOTRESET | OUTPUT | P15 | | QA | OUTPUT | P16 | | QB | OUTPUT | P17 | | QC | OUTPUT | P18 | | QD | OUTPUT | P19 | | RESET | INPUT | P71 | +------------------------------------------------+-----------+--------------+ | Dedicated or Special Pin Name | Pin Number | +------------------------------------------------------------+--------------+ | /PROG | P55 | | CCLK | P73 | | DONE | P53 | | GND | P21 | | GND | P1 | | GND | P52 | | GND | P76 | | GND | P43 | | GND | P31 | | GND | P64 | | GND | P12 | | M0 | P32 | | M1 | P30 | | M2 | P34 | | TDO | P75 | | TDO | TDO | | VCC | P33 | | VCC | P2 | | VCC | P42 | | VCC | P63 | | VCC | P11 | | VCC | P54 | | VCC | P74 | | VCC | P22 | +------------------------------------------------------------+--------------+ Pinout by Pin Number: +--------------+-----------------------------------+-----------+------------+ | Pin Number | Pin Name | Direction | Constraint | +--------------+-----------------------------------+-----------+------------+ | P1 | GND | | | | P2 | VCC | | | | P3 | | | | | P4 | | | | | P5 | | | | | P6 | | | | | P7 | | | | | P8 | | | | | P9 | | | | | P10 | | | | | P11 | VCC | | | | P12 | GND | | | | P13 | | | | | P14 | | | | | P15 | NOTRESET | OUTPUT | LOCATED | | P16 | QA | OUTPUT | LOCATED | | P17 | QB | OUTPUT | LOCATED | | P18 | QC | OUTPUT | LOCATED | | P19 | QD | OUTPUT | LOCATED | | P20 | | | | | P21 | GND | | | | P22 | VCC | | | | P23 | | | | | P24 | | | | | P25 | | | | | P26 | | | | | P27 | | | | | P28 | | | | | P29 | | | | | P30 | M1 | | | | P31 | GND | | | | P32 | M0 | | | | P33 | VCC | | | | P34 | M2 | | | | P35 | | | | | P36 | | | | | P37 | | | | | P38 | | | | | P39 | | | | | P40 | | | | | P41 | CLK | INPUT | LOCATED | | P42 | VCC | | | | P43 | GND | | | | P44 | | | | | P45 | | | | | P46 | | | | | P47 | | | | | P48 | | | | | P49 | | | | | P50 | | | | | P51 | | | | | P52 | GND | | | | P53 | DONE | | | | P54 | VCC | | | | P55 | /PROG | | | | P56 | | | | | P57 | | | | | P58 | | | | | P59 | | | | | P60 | | | | | P61 | | | | | P62 | | | | | P63 | VCC | | | | P64 | GND | | | | P65 | | | | | P66 | | | | | P67 | | | | | P68 | | | | | P69 | | | | | P70 | | | | | P71 | RESET | INPUT | LOCATED | | P72 | | | | | P73 | CCLK | | | | P74 | VCC | | | | P75 | TDO | | | | P76 | GND | | | | P77 | | | | | P78 | | | | | P79 | | | | | P80 | | | | | P81 | | | | | P82 | | | | | P83 | | | | | P84 | | | | | TDO | TDO | | | +--------------+-----------------------------------+-----------+------------+ # # Pinout constraints listing # These constraints are in PCF grammar format # and may be cut and pasted into the PCF file # after the "SCHEMATIC END ;" statement to # preserve this pinout for future design iterations. # COMP "CLK" LOCATE = SITE "P41" ; COMP "NOTRESET" LOCATE = SITE "P15" ; COMP "QA" LOCATE = SITE "P16" ; COMP "QB" LOCATE = SITE "P17" ; COMP "QC" LOCATE = SITE "P18" ; COMP "QD" LOCATE = SITE "P19" ; COMP "RESET" LOCATE = SITE "P71" ; #