PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. par -w -ol 2 -d 0 map.ncd demo.ncd demo.pcf Constraints file: demo.pcf Loading device database for application par from file "map.ncd". "demo" is an NCD, version 2.27, device xc4005e, package pc84, speed -4 Loading device for application par from file '4005e.nph' in environment C:/fndtn. Device speed data version: x1_0.95 PRELIMINARY. Resolved that IOB must be placed at site P41. Place IOB CLK in site P41. Resolved that IOB must be placed at site P15. Place IOB NOTRESET in site P15. Resolved that IOB must be placed at site P16. Place IOB QA in site P16. Resolved that IOB must be placed at site P17. Place IOB QB in site P17. Resolved that IOB must be placed at site P18. Place IOB QC in site P18. Resolved that IOB must be placed at site P19. Place IOB QD in site P19. Resolved that IOB must be placed at site P71. Place IOB RESET in site P71. Device utilization summary: Number of External IOBs 7 out of 61 11% Flops: 0 Latches: 0 Number of CLBs 3 out of 196 1% Total CLB Flops: 5 out of 392 1% 4 input LUTs: 4 out of 392 1% 3 input LUTs: 2 out of 196 1% Overall effort level (-ol): 2 (set by user) Placer effort level (-pl): 2 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 2 (default) Starting initial Placement phase. REAL time: 19 secs Finished initial Placement phase. REAL time: 20 secs Starting Constructive Placer. REAL time: 20 secs Finished Constructive Placer. REAL time: 20 secs Writing design to file "demo.ncd". Starting Optimizing Placer. REAL time: 20 secs Optimizing Swapped 31 comps. Xilinx Placer [1] 3600 REAL time: 21 secs Finished Optimizing Placer. REAL time: 21 secs Writing design to file "demo.ncd". Total REAL time to Placer completion: 21 secs Total CPU time to Placer completion: 0 secs 0 connection(s) routed; 26 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 21 secs Starting iterative routing. Routing active signals. End of iteration 1 26 successful; 0 unrouted; (0) REAL time: 22 secs Constraints are met. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "demo.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 26 successful; 0 unrouted; (0) REAL time: 26 secs Writing design to file "demo.ncd". Total REAL time: 26 secs Total CPU time: 0 secs End of route. 26 routed (100.00%); 0 unrouted. No errors found. Completely routed. This design was run without timing constraints. It is likely that much better circuit performance can be obtained by trying either or both of the following: - Enabling the Delay Based Cleanup router pass, if not already enabled - Supplying timing constraints in the input design Total REAL time to Router completion: 26 secs Total CPU time to Router completion: 0 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 368 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 3.090 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.256 ns The Maximum Pin Delay is: 8.193 ns The Average Connection Delay on the 10 Worst Nets is: 2.972 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 26 0 0 0 0 0 Writing design to file "demo.ncd". All signals are completely routed. Total REAL time to PAR completion: 28 secs Total CPU time to PAR completion: 0 secs PAR done.