No known errata
No known errata
Page 2-6
Page 2-7, section 2.1.3.2
- Spelling of complement incorrect
Page 4-4, table 4.3
- Parameter twait4 should also specify "from READYbar high"
Page 4-5, table 4.4
- Parameter td2 is from DATA IN valid, not data invalid
Page 4-6, table 4.5
- Parameter twait is relative to READYbar low not Rbar low
Page 2 of 8, section 2
- The data transfer starts after a 320µs wait, not 320ns as shown.
- A wait period of 100ns at 160kHz would be 80ns at 200kHz, not 20ns as shown.
Page 3 of 8, section 2
- The 4 address bits in C & D can be thought of as an extension of the address register, not address resistor.
Page 5 of 8, section 3
- The limits of Vdd should be -9.3 (min) -9 (nom) -9.7 (max).
- Parameter tch1h is the delay time for M0 or M1, not I0 or I1.